Guna Bala Shekar, Head - India Sales and Business Development, LSI India Research & Development Pvt. Ltd.

Mobile broadband is taking off in a big way, driven by smartphones, tablets, cloud services, and apps. In addition to these devices, there is increasingly an internet of things consisting of sensors, cameras, and other devices connected to mobile network. All of these result in massive traffic growth, creating a data deluge that is straining the network. Contending with data deluge requires equipment that can deliver greater bandwidth to the user with fine-grained traffic management that can help operators recognize and prioritize important traffic.

Unmanaged, all these factors add further strain to the entire mobile infrastructure, especially in the packet core. At the same time, with all data plans and declining voice traffic, the ARPU (average revenue per user) is going down drastically. Mobile operators are struggling to offer products at price points that would justify their investments. Hence, it is critical that packet processing devices used in the equipment have to be engineered to operate at the right performance and power with costs that make sense.

Packet Processing Architectures

Packet processors targeted toward these applications fall under three different categories. They are non-pipelined, pipelined, and other alternative architectures.

The non-pipelined architecture has a huge dependence on the CPU for arbitrating the next step in a packet sequence. Incoming packets are of different types and each of them needs a different set of operations performed on them. For example, an incoming IPSEC packet that is segmented has to be CRC checked, classified, reassembled, classified again, decrypted, authenticated, and finally scheduled as per its SLA (service level agreement). If the CPU has to take the decision for every single step, it consumes a large number of available processing cycles. Most of the time, system architects are faced with this big challenge of processing all different types of incoming packets with fine-grained traffic management while at the same time leaving enough cycles available to process interrupts, exceptions, and future feature additions. Although CPU performance is steadily increasing, it can still be the bottleneck in a non-pipelined architecture.

A pipelined architecture works well for applications where the majority of packets follow a predefined path through the device. A classic example would be an L2/L3 switch. In applications where different packets or flows follow different processing sequences, this architecture does not work well. System architects are now increasingly opting for alternative architectures that combine the programmable flexibility of general-purpose CPU cores and the determinism and power efficiency of hardware acceleration engines. For example, a virtual pipelined architecture eliminates the CPU bottleneck by moving the decision for the next step in the processing chain to individual hardware acceleration engines. This complete offload frees up the available cycles in the CPU to be used for exception processing as well as future feature additions.

EPC Application

The LTE EPC (evolved packet core) architecture delineates the data and controls planes clearly with distinct performance expectations on both. Packet processors used in such equipment need to be flexible enough to support these bandwidths with a right feature set that allows the equipment vendor to offer sophisticated traffic management to mobile operators, thereby enabling them to apply right SLA policies at the user, application, and flow levels. Besides the traditional packet cores that cater to millions of users, there is also a requirement for a lighter version of the evolved packet core that caters to load balancing the demands of thousands of users across rapidly deploying hierarchical heterogeneous networks. These smaller clouds need a lighter version of the EPC that closely ties in with features required by the users with custom-designed LTE handsets.

Conclusion

Data deluge is placing increasing demands on the networks. It is clear that mobile packet core design poses the biggest challenge for wireless system architects and there is a need for packet processors with flexible architectures to support fine grain control and complex design requirements. These packet processors should not only meet the current throughput requirements of these applications but should also provide enough headroom to allow the equipment manufacturer to evolve their network to provide feature upgrades without changing the underlying hardware.