C‑DAC gears up for debut of chiplet technology by FY27

C-DAC is set to unveil its first home-grown chiplet technology demonstrator by Q1 FY27.​

The chiplet demonstrator will be designed and validated entirely in India using a mix of indigenous IP cores and globally licensed Electronic Design Automation (EDA) tools. While fabrication may initially rely on international foundries, the packaging and integration—key steps in achieving system-level interoperability—will be carried out locally through C-DAC’s national semiconductor research infrastructure including its ChipIN Centre in Bengaluru.

C‑DAC’s move aligns with India’s long-term goal to build local capability in heterogeneous integration and advanced chip packaging. The project will serve as a proof‑of‑concept platform for future chiplet-based processors that can mix computing, networking, and AI acceleration cores — similar to modern designs from AMD and Intel but using domestic design talent and test infrastructure. The initiative is expected to play an anchor role in India’s Chips to Startup (C2S)program, which aims to train over 85,000 semiconductor engineers and researchers by 2027.​

CT Bureau